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gs841e18at/b-180/166/150/130/100 256k x 18 sync cache tag 180 mhz?100 mhz 3.3 v v dd 3.3 v and 2.5 v i/o tqfp, bga commercial temp industrial temp rev: 1.03 4/2005 1/21 ? 2001, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. * pentium is a trademark of intel features ? 3.3 v +10%/?5% core power supply, 2.5 v or 3.3 v i/o supply ? dual cycle deselect (dcd) ? intergrated data comparator for tag ram application ? ft mode pin for flow through or pipeline operation ? lbo pin for linear or interleave (pentium tm and x86) burst mode ? synchronous address, data i/o, and control inputs ? synchronous data enable (de ) ? asynchronous output enable (oe ) ? asynchronous match output enable (moe ) ? byte write (bwe ) and global write (gw ) operation ? three chip enable signals for easy depth expansion ? internal self-timed write cycle ? jtag test mode conforms to ieee standard 1149.1 ? jedec-standard 100-lead tqfp package and 119-bga ? pb-free 100-lead tqfp package available functional description the gs841e18a is a 256k x 18 hi gh performance synchronous dcd sram with integrated tag ram comp arator. a 2-bit burst counter is included to provide burst interface with pentium tm and other high performance cpus. it is designed to be used as a cache tag sram, as well as data sram. addresse s, data ios, ma tch output, chip enables (ce1 , ce2, ce3 ), address control inputs (adsp , adsc , adv ), and write control inputs (bw1 , bw2 , bwe , gw, de ) are synchronous and are controlled by a positive-edge-triggered clock (clk). output enable (oe ), match output enable , and power down control (zz) are asynchronous. bu rst can be initiated with either adsp or adsc inputs. subsequent burst addres ses are generated internally and are controlled by adv . the burst sequence is e ither interleave order (pentium tm or x86) or linear order, and is controlled by lbo . output registers and the match output register are provided and controlled by the ft mode pin (pin 14). through use of the ft mode pin, i/o registers can be program med to perform pipeline or flow through operation. flow thr ough mode reduces latency. byte write operation is performed by using byte write enable (bwe ) input combined with two indi vidual byte write signals bw 1-2. in addition, global write (gw ) is available for writing all bytes at one time. compare cycles begin as a read cycle with output disabled so that compare data can be loaded into the data input register. the comparator compares the read data w ith the registered input data and a match signal is generated. the match output can be either in pipeline or flow through modes controlled by the ft signal. low power (standby mode) is attained through the assertion of the zz signal, or by stopping the clock (clk ). memory data is retained during standby mode. jtag boundary scan interface is provided using ieee standard 1149.1 protocol. four pins?test da ta in (tdi), test data out (tdo), test cloc k (tck) and test mode select (tms)?are used to perform jtag function. the gs841e18a operates on a 3.3 v power supply and all inputs/ outputs are 3.3 v- or 2.5 v-lvtt l-compatible. separate output (v ddq ) pins are used to allow both 3.3 v or 2.5 v io interface. dual cycle deselect (dcd) the gs841e18a is a dcd pipe lines synchronous sram. dcd srams pipeline disabl e commands to the same degree as read commands. dcd srams hold the de select command for one full cycle and then begin turning off their outputs just after the second rising edge of the clock. parameter synopsis ?180 -166 -150 -133 -100 pipeline 3-1-1-1 t cycle t kq i dd 5.5 ns 3.2 ns 335 ma 6.0 ns 3.5 ns 310 ma 6.6 ns 3.8 ns 275 ma 7.5 ns 4.0 ns 250 ma 10 ns 4.5 ns 190 ma flow through 2-1-1-1 t kq t cycle i dd 8 ns 9.1 ns 210 ma 8.5 ns 10 ns 190 ma 10 ns 10 ns 190 ma 11 ns 15 ns 140 ma 12 ns 15 ns 140 ma
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 2/21 ? 2001, gsi technology pin configurat ion (package t) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss d dq v ss v ddq dq dq v dd nc v ss dq dq v ddq v ss dq dq dq p v ss v ddq v ddq v ss dq dq v ss vddq dq dq v ss nc v dd zz dq dq v ddq v ss dq dq v ss v ddq lbo a a a a a 1 a 0 tms tdi v ss v dd tdo tck a a a a a a a a ce 1 ce 2 nc nc bw 2 bw 1 ce 3 clk gw bwe v dd v ss oe adsc adsp adv a a a 256k x 18 top view dq p a nc nc nc nc nc de match moe nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ft
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 3/21 ? 2001, gsi technology gs841e18a padout?119-bump bga?top view (package b) 1234567 a v ddq a a adsp aav ddq b nc e 2 aadsc ae 3 nc c nc a a v dd aanc d dq b nc v ss nc v ss dq p nc e nc dq b v ss e 1 v ss nc dq a f v ddq nc v ss g v ss dq a v ddq g nc d q b b b adv nc nc dq a h dq b n c v ss gw v ss dq a nc j v ddq v dd nc v dd nc v dd v ddq k nc dq b v ss ck v ss nc dq a l dq b nc nc nc b a dq a nc m v ddq dq b v ss bw v ss match v ddq n dq b nc v ss a 1 v ss dq a de p nc dq p v ss a 0 v ss moe dq a r nc a lbo v dd ft anc t nc a a nc a a zz u v ddq tms tdi tck tdo nc v ddq
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 4/21 ? 2001, gsi technology tqfp pin description symbol description an address input signals?inputs are registered and mu st meet setup and hold times, as specified on page 11 . clk clock input signal bwe byte write enable signal?the byte write enable si gnal needs to be combined with one of the four byte write signals for a write operation to occur. bw1 byte write signal for data outputs 1 thru 8 bw2 byte write signal for data outputs 9 thru 16 gw global write enable ce1 ,ce2, ce3 chip enables oe output enable adv burst address advance adsp , adsc address status signals dq data input and output pins dqp parity input and output pins match match output moe match output enable de data enable?data input registers are updated only when de is active. zz power down control?application of zz will result in a low standby power consumption. ft flow through or pipeline mode lbo linear order burst mode tms test mode select tdi test data in tdo test data out tck test clock v dd 3.3 v power supply v ss ground v ddq 2.5 v/3.3 v output power supply nc no connect
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 5/21 ? 2001, gsi technology pbga pin description symbol description an address input signals?inputs are registered and must meet setup and hold times, as specified on page 11 . clk clock input signal bwe byte write enable signal?the byte write enable si gnal needs to be combined with one of the four byte write signals for a write operation to occur. bw1 byte write signal for data outputs 1 thru 8 bw2 byte write signal for data outputs 9 thru 16 gw global write enable ce1 ,ce2, ce3 chip enables oe output enable adv burst address advance adsp , adsc address status signals dq data input and output pins dqp parity input and output pins match match output moe match output enable de data enable?data input r egisters are updated only when de is active. zz power down control?application of zz will result in a low standby power consumption. ft flow through or pipeline mode lbo linear order burst mode tms test mode select tdi test data in tdo test data out tck test clock v dd 3.3 v power supply v ss ground v ddq 2.5 v/3.3 v output power supply nc no connect
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 6/21 ? 2001, gsi technology functional block diagram a1 a0 a0 a1 d0 d1 q1 q0 b inary c ounter load dq r egiste r dq register dq register dq register dq register dq register dq register d q register a0-17 lbo adv clk adsc adsp gw bwe bw1 bw2 ce1 ce2 ce3 ft dq1-16 oe zz powerdown control 256k x 18 memory array 18 18 18 18 2 18 a qd dqp1-2 de dq register match tap controller instruction reg. id reg. bypass reg boundary scan registers 54 tck tms tdi a, dq, control tdo moe always (?)
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 7/21 ? 2001, gsi technology mode pin function lbo function l linear burst h or nc interleaved burst ft function l flow through h or nc pipeline power down control note: there are pull up devices on lbo and ft pins and pull down device on zz pin, so those input pins can be unconnected and the chip will operate in the default states as sp ecified in the above tables. zz function l or nc active h standby, idd = isb linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 note: h = logic high, l = logic low, nc = no connect byte write function function gw bwe bw1 bw2 read h h x x read h l h h write all bytes l x x x write all bytes h l l l write byte 1 h l l h write byte 2 h l h l
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 8/21 ? 2001, gsi technology notes: 1. x means ?don?t care,? h means ?logic high,? l means ?logic low.? 2. write is the logic function of gw , bwe , bw1 , bw2 . see byte write function table for detail. 3. all inputs, except oe , must meet setup and hold on rising edge of clk. 4. suspending busrt generates a wait cycle. 5. adsp low along with sram being selected always initiate s a read cycle at the l-h edge of the clock (clk). 6. a write cycle can only be performed by setting write low for the clock l-h edge of the subsequent wait cycle. refer to page 12 for the write timing diagram. synchronous truth table operation address used ce1 ce2 ce3 adsp adsc adv write oe clk dq deselect cycle, power down none h x x x l x x x l-h high-z deselect cycle, power down none l l x l x x x x l-h high-z deselect cycle, power down none l x h l x x x x l-h high-z deselect cycle, power down none l l x h l x x x l-h high-z deselect cycle, power down none l x h h l x x x l-h high-z read cycle, begin burst external l h l l x x x l l-h q read cycle, begin burst e xternal l h l l x x x h l-h high-z read cycle, begin burst external l h l h l x h l l-h q read cycle, begin burst e xternal l h l h l x h h l-h high-z write cycle, begin burst external l h l h l x l x l-h d read cycle, continue burst next x x x h h l h l l-h q read cycle, continue burst next x x x h h l h h l-h high-z read cycle, continue burst next h x x x h l h l l-h q read cycle, continue burst next h x x x h l h h l-h high-z write cycle, continue burst next x x x h h l l x l-h d write cycle, continue burst next h x x x h l l x l-h d read cycle, suspend burst current x x x h h h h l l-h q read cycle, suspend burst current x x x h h h h h l-h high-z read cycle, suspend burst current h x x x h h h l l-h q read cycle, suspend burst current h x x x h h h h l-h high-z write cycle, suspend burst current x x x h h h l x l-h d write cycle, suspend burst current h x x x h h l x l-h d
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 9/21 ? 2001, gsi technology notes: 1. x means ?don?t care,? h means ?logic high,? l means ?logic low.? 2. write is the logic function of gw , bwe , bw1 , bw2 . see byte write function table for detail. 3. ce is defined as ce1 =l, ce2=h and ce3 =l 4. all signals are synchronous and ar e sampled by clk except oe and moe . oe and moe are asynchronous and drive the bus immediately. ) note: permanent damage to the device may occur if the absolute maximun ratings are exceeded. functional operation should be restricte d to the recommended operation conditions. ex posure to higher than recommended voltages, for an extended period of time, could effect th e performance and reliability of this component. truth table for read/write/c ompare/fill write operation ce write de moe oe match dq read l h x x l ? q write lllxh?d compare l h l l h data out d fill write l l h x x ? x match deselect h x x l x high high z deselect h x x h x high z high z absolute maximum ratings (voltage reference to v ss = 0 v) symbol description commerical unit v dd supply voltage ?0.5 to 4.6 v v ddq output supply voltage ?0.5 to v dd v v clk clk input voltage ?0.5 to 6 v v in input voltage ?0.5 to v dd + 0.5 ( 4.6 v max. ) v v out output voltage ?0.5 to v dd + 0.5 ( 4.6 v max. ) v i out output current per i/o +/?20 ma p d power dissipation 1.5 w t opr operating temperature 0 to 70 o c t stg storage temperature ?55 to 125 o c
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 10/21 ? 2001, gsi technology notes: 1. junction temperature is a function of sr am power dissapation, package thermal resi stance, mounting board temperature, ambient . temperature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87. 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1. package thermal characteristics rating layer board symbol tqfp max pbga max unit notes junction to ambient (at 200 lfm) single r ja 32 28 c/w 1,2 junction to ambient (at 200 lfm) four r ja 20 18 c/w 1,2 junction to case (top) ? r jc 74 c/w 3 notes: 1. include scope and jig capacitance. 2. test conditions as specified wi th output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz . 4. device is deselected as defined by the truth table. ac test conditions (vdd = 3.135 v?3.6 v, ta = 0?70 c) parameter conditions input high level v ih = 2.3 v input low level v il = 0.2 v input slew rate tr = 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 dq vt = 1.25 v 5 0w 30pf 1 dq 2.5 v f ig . 1 output load 1 output load 2 f ig . 2 225w 225w 5pf 1
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 11/21 ? 2001, gsi technology dc characteristics and supply currents (voltage reference to v ss = 0 v) (vdd = 3.135 v?3.6 v, ta = 0?70 c for commercial temperature offering) parameter symbol test conditions min max input leakage current (except zz, ft , lbo pins) i il v in = 0 to v dd ?1 ua 1 ua zz input current iin zz v dd v in v ih 0 v v in v ih ?1 ua ?1 ua 1 ua 300 ua mode input current (ft & lbo pins) iin m v dd v in v il 0 v v in v il ?30 0ua ?1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ?4 ma, v ddq = 2.375 v 1.7 v output high voltage v oh i oh = ?4 ma, v ddq = 3.135 v 2.4 v output low voltage v ol i ol = +4 ma 0.4 v
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 12/21 ? 2001, gsi technology operating currents parameter test conditions symbol -180 -166 -150 -133 -100 unit 0 to 70c ?40 to 85c 0 to 70 c ?40 to +85 c 0 to 70 c ?40 to +85 c 0 to 70 c ?40 to +85 c 0 to 70 c ?40 to +85 c o perating current device selected; all other inputs v ih o r v il output open i dd pipeline 335 345 310 320 275 285 250 260 190 200 ma i dd flow through 210 220 190 200 190 200 140 150 140 150 ma standby current zz v dd ? 0.2 v i sb pipeline 20 30 30 40 30 40 30 40 30 40 ma i sb flow through 20 30 30 40 30 40 30 40 30 40 ma deselect supply current device deselected; all other inputs v ih or v il i dd pipeline 55 65 110 120 105 115 100 110 80 90 ma i dd flow through 40 50 80 90 80 90 65 75 65 75 ma
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 13/21 ? 2001, gsi technology notes: 1. these parameters are sampled and are not 100% tested 2. zz is an asynchronous signal. however, in order to be recogniz ed on any given clock cycle, zz mu st meet the specified setup a nd hold times as specified above. ac electrical characteristics parameter symbol -180 -166 -150 -133 -100 unit min max min max min max min max min max pipeline clock cycle time tkc 5.5 ? 6.0 ? 6.7 ? 7.5 ? 10 ? ns clock to output valid tkq ? 3.2 ? 3.5 ? 3.8 ? 4 ? 4.5 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to match valid tkm ? 3.2 ? 3.5 ? 3.8 ? 4 ? 4.5 ns clock to match invalid tkmx 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to match in low-z tmlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow through clock cycle time tkc 9.1 ? 10.0 ? 10.0 ? 15.0 ? 15.0 ? ns clock to output valid tkq ? 8.0 ? 8.5 ? 10.0 ? 11.0 ? 12.0 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to match valid tkm ? 8.5 ? 8.5 ? 10.0 ? 11.0 ? 12.0 ns clock to match invalid tkmx 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to match in low-z tmlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.3 ? 1.5 ? 1.7 ? 2 ? ns clock low time tkl 1.5 ? 1.5 ? 1.7 ? 1.9 ? 2.2 ? ns clock to output in high-z thz 1 1.5 3.2 1.5 3.5 1.5 3.8 1.5 4 1.5 5 ns oe to output valid toe ? 3.2 ? 3.5 ? 3.8 ? 4 ? 5 ns oe to output in low-z tolz 1 0?0?0?0?0?ns oe to output in high-z tohz 1 ?3.2?3.5?3.8? 4 ? 5 ns moe to match valid tmoe ? 3.2 ? 3.5 ? 3.8 ? 4 ? 5 ns moe to match in low-z tmolz 1 0?0?0?0?0?ns moe to match in high-z tmohz 1 ?3.2?3.5?3.8? 4 ? 5 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 2.0 ? 2.0 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5?5?5?5?5?ns zz hold time tzzh 2 1?1?1?1?1?ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? 20 ? ns
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 14/21 ? 2001, gsi technology pipeline mode timing begin read a cont deselect deselect write b read c read c+1 read c+2 read c+3 cont deselect deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts ts th ts th ts th ts tkc tkc tkl tkl tkh tkh q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) abc hi-z deselected with e1 e2 and e3 only sampled with adsc adsc initiated read ck adsp adsc adv ao?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 15/21 ? 2001, gsi technology flow through mode timing begin read a cont deselect write b read c read c+1 read c+2 read c+3 read c deselect thz tkqx tlz th ts tohz toe tkq th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh abc q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) q(c) e2 and e3 only sampled with adsp and adsc e1 masks adsp adsc initiated read deselected with e1 e1 masks adsp fixed high ck adsp adsc adv ao?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 16/21 ? 2001, gsi technology pipeline compare fill write cycle hit miss fill write a b b a a tkm tkm tkmx tkm tmoe tmlz th ts th ts th ts th ts th ts k address dq ce w g de moe match
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 17/21 ? 2001, gsi technology flow through compare fill write cycle hit miss fill write a b b a a tkm tkm tkmx tkm tmoe tmlz th ts th ts th ts th ts th ts k address dq ce w g de moe match
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 18/21 ? 2001, gsi technology tqfp package drawing (package t) d1 d e1 e pin 1 b e c l l1 a2 a1 y notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity 0.10 lead angle 0 ? 7
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 19/21 ? 2001, gsi technology package dimensions?119-bump fpbga (package b, variation 2 ) a b c d e f g h j k l m n p r t u 1 2 3 4 5 6 7 7 6 5 4 3 2 1 a1 top view a1 bottom view 1.27 7.62 1.27 20.32 140.10 220.10 b a 0.20(4x) ?0.10 ?0.30 c c a b s s ?0.60~0.90 (119x) c seating plane 0.15 c 0.50~0.70 1.86.0.13 0.700.05 0.15 c a b c d e f g h j k l m n p r t u 0.560.05 s s
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 20/21 ? 2001, gsi technology ordering information org part number 1 type package speed 2 (mhz/ns) t a 3 status 256k x 18 gs841e18at-180 dcd pipeline/flow through tqfp 180/8 c 256k x 18 GS841E18AT-166 dcd pipeline/flow through tqfp 166/8.5 c 256k x 18 gs841e18at-150 dcd pipeline/flow through tqfp 150/10 c 256k x 18 gs841e18at-133 dcd pipeline/flow through tqfp 133/11 c 256k x 18 gs841e18at-100 dcd pipeline/flow through tqfp 100/12 c 256k x 18 gs841e18at-180i dcd pipeline/flow through tqfp 180/8 i 256k x 18 GS841E18AT-166i dcd pipeline/flow through tqfp 166/8.5 i 256k x 18 gs841e18at-150i dcd pipeline/flow through tqfp 150/10 i 256k x 18 gs841e18at-133i dcd pipeline/flow through tqfp 133/11 i 256k x 18 gs841e18at-100i dcd pipeline/flow through tqfp 100/12 i 256k x 18 gs841e18agt-180 dcd pipeline/flow through pb-free tqfp 180/8 c 256k x 18 gs841e18agt-166 dcd pipeline/flow through pb-free tqfp 166/8.5 c 256k x 18 gs841e18agt-150 dcd pipeline/flow through pb-free tqfp 150/10 c 256k x 18 gs841e18agt-133 dcd pipeline/flow through pb-free tqfp 133/11 c 256k x 18 gs841e18agt-100 dcd pipeline/flow through pb-free tqfp 100/12 c 256k x 18 gs841e18agt-180i dcd pipeline/flow through pb-free tqfp 180/8 i 256k x 18 gs841e18agt-166i dcd pipeline/flow through pb-free tqfp 166/8.5 i 256k x 18 gs841e18agt-150i dcd pipeline/flow through pb-free tqfp 150/10 i 256k x 18 gs841e18agt-133i dcd pipeline/flow through pb-free tqfp 133/11 i 256k x 18 gs841e18agt-100i dcd pipeline/flow through pb-free tqfp 100/12 i 256k x 18 gs841e18ab-180 dcd pipeline/flow through 119 bga (var. 2) 180/8 c 256k x 18 gs841e18ab-166 dcd pipeline/flow through 119 bga (var. 2) 166/8.5 c 256k x 18 gs841e18ab-150 dcd pipeline/flow through 119 bga (var. 2) 150/10 c 256k x 18 gs841e18ab-133 dcd pipeline/flow through 119 bga (var. 2) 133/11 c 256k x 18 gs841e18ab-100 dcd pipeline/flow through 119 bga (var. 2) 100/12 c 256k x 18 gs841e18ab-180i dcd pipeline/flow through 119 bga (var. 2) 180/8 i 256k x 18 gs841e18ab-166i dcd pipeline/flow through 119 bga (var. 2) 166/8.5 i 256k x 18 gs841e18ab-150i dcd pipeline/flow through 119 bga (var. 2) 150/10 i 256k x 18 gs841e18ai-133i dcd pipeline/flow through 119 bga (var. 2) 133/11 i 256k x 18 gs841e18ab-100i dcd pipeline/flow through 119 bga (var. 2) 100/12 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs841e18at -166t. 2. the speed column indicates the cycle frequ ency (mhz) of the device in pipelined mode and the latency (ns) in flow through mo de. each device is pipeline / flow thr ough mode selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gsi technology w eb site for a complete listing of current offerings.
gs841e18at/b-180/166/150/130/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.03 4/2005 21/21 ? 2001, gsi technology 4mb synchronous tag ram da tasheet revision history rev. code: old;new types of changes format or content page /revisions;reason gs841e18a_r1 ? creation of new datasheet gs841e18a_r1; gs841e18a_r1_01 content ? moved tck from u6 (incorrect placement) to u4 (correct placement) on bga ? changed u6 to nc gs841e18a_r1_01; gs841e18a_r1_02 format/content ? updated format ? added 180 mhz speed bin ? updated timing diagrams ? updated mechanical drawings ? added pb-free info for tqfp gs841e18a_r1_02; gs841e18a_r1_03 content ? added pipeline compare fill wr ite cycle and flow through compare fill write c ycle timing diagrams

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